Search engine systems may typically include a device for comparing search keys (also called comparands) with a number of stored data values. Do to the rapid matching capabilities of content addressable memories (CAMs), search engine systems can include one or more CAM devices. A CAM device can include circuitry for performing one or more types of search operations. In a search operation, a comparand (or key) may be compared to multiple entries to see if all or a portion of the key matches an entry. After a search operation, a CAM device may give a search result as an output. Typically a search result may include an “index” value that may be used to access associated data.
Because storing associated data on a CAM device itself may consume undue device area, it may be desirable to provide one or more memory devices, such as random access memory (RAM) devices to store such associated data.
To better understand the various features and aspects of search engine systems that may include RAM devices, a number of conventional search engine systems will now be described.
A first conventional search engine system is shown in FIG. 34 and designated by the general reference character 3400. A conventional search engine system 3400 may include a host 3402, one or more CAM devices 3404, and a RAM sub-system 3406. A RAM sub-system 3406 may include RAM devices 3406-0 to 3406-i. A host device 3402 may include one or more processor devices, and may issue search commands for a system, as well as receive search result data. In the particular example of FIG. 34, a host 3402 may issue search commands to a CAM device 3404. In response to such commands, a CAM device 3404 may provide data, such as an index value to a host 3402. A host 3402 may then access one of the RAM devices 3406-0 to 3406-i to retrieve associated data. In some conventional approaches, an index value provided by a CAM device 3404 may be a portion of an address for accessing an entry of a RAM device (3406-0 to 3406-i).
A host 3402 may also have to continually update associated data. Such “housekeeping” operations can typically involve common operations on a range of addresses.
Referring now to FIG. 34, a typical conventional RAM device (3406-0 to 3406-i) may include a chip select input CS, address inputs (A0-An), and data input/outputs (I/Os) (D0-Dx). As is well understood, a conventional RAM device (3406-0 to 3406-i) can be enabled according to logic at a corresponding chip select input CS.
Address inputs (A0-An) of RAM devices (3406-0 to 3406-i) can be commonly connected to an address bus 3408 and data I/Os (D0-Dx) can be commonly connected to a data bus 3412. Each chip select input CS can be connected to a different chip select line. Such different chip select lines are shown in FIG. 34 as item 3410.
Thus, in order to read associated data, a host 3402 may activate one of chip select lines 3410 and drive an address value on address bus 3408. In response, the RAM device (3406-0 to 3406-i) receiving that active chip select signal may drive data bus 3412 with data stored at the supplied address. Similarly, in order to update associated data in a RAM device (3406-0 to 3406-i), a host 3402 may activate one of chip select lines 3410 and drive an address value on address bus 3408 and write data on data bus 3412. In response, the RAM device (3406-0 to 3406-i) receiving that active chip select signal can store data on data bus 3412 at the supplied address.
While FIG. 34 illustrates an arrangement in which a host 3402 may generate addresses for accessing associated data, alternate conventional approaches may include arrangements in which a CAM device may issue such addresses. One such conventional approach is shown in FIG. 35 and designated by the general reference character 3500. A system 3500 may include a host 3502, one or more CAM devices 3504 and a RAM sub-system 3506. Unlike the arrangement of FIG. 34, in FIG. 35, a CAM device 3504 may apply address and control signals to a RAM sub-system to thereby place associated data on a data bus 3508.
An important feature of many CAM based systems can be the rate at which associated data may be generated and/or updated. Consequently, it is desirable to increase the overall rate at which associated data values within such RAM devices can be accessed and updated.
A drawback to conventional approaches, like those shown in FIGS. 34 and 35 can be the complexity in, and/or lack in uniformity of connections to such RAM devices (3406-0 to 3406-i). As associated data amounts are increased, a number or capacity of RAM devices (3406-0 to 3406-i) may also increase. In the latter case, more and more address lines may be needed and corresponding RAM devices may have to include additional address inputs. Additional address inputs can increase system layout space. Larger address inputs (i.e., chip pinouts) may increase component cost.
In the event RAM device numbers are increased, it may be increasingly difficult to layout chip select lines, or the like, to have a same signal latency, as each chip select line may have a separate route and/or different loading than shared address or data bus lines. As a result, in order to achieve as high a processing rate as possible, a host may have to adapt to different delays between RAM devices, as such delays may depend on a RAM device's location with respect to a host. Still further, RAM device speeds (the speed at which data may be written or read) can also vary, adding to the complexity of a host operation.
Yet another drawback to conventional approaches, like that of FIG. 34, can be added difficulty or complexity in supporting multiprocessor and/or multithreaded environments. In such environments it can be desirable for one processor (or thread) to accesses a given memory device to perform an operation while other processors (or threads) compete for a same memory device and/or a common bus that accesses such memory devices. In such an environment, it can be difficult to implement methods of controlling access to memory devices, such as a method that can “lock” an access path between a processor (or thread) and a memory device, or methods that attempt to maintain a cache coherence for accesses by multiple processors (or threads) to a common memory space.
The IEEE Scalable Coherent Interface (I.E.E.E. Standard 1596-1992), referred to herein as SCI, discloses an interface for providing the higher throughput needed in multiprocessor systems. Such an interface may include point-to-point links between SCI nodes. An example of such an SCI node is shown in FIG. 36, and designated by the general reference character 3600. An SCI node 3600 may include an output multiplexer (MUX) that may receive data from a bypass first-in-first-out (FIFO) memory and output FIFO. SCI also discloses arrangements in which a grid of processors may be interconnected by rings. In such a configuration, each processor may include two SCI nodes.
An example of an SCI request packet is set forth in FIG. 37, and designated by the general reference character 3700. A request packet may include a target field (targetId), a command field (command), source field (sourceId), and an error check field (CyclicRedundancyCode (CRC)). Thus, an SCI request packet may have a minimum size of 16 bytes.
Within an SCI packet, a target field may include 16 bits that can indicate a designated destination for a request. A command field may also include sixteen bits, and is shown in more detail in FIG. 37. A command field may include a 7 bit portion, shown as “cmd(<124)” that can specify a particular operation to be performed.
An SCI command can include response expected commands (see SCI, Page 69, Table 3-8) and responseless-subaction commands (see SCI, Page 70, Table 3-9). Such responseless-subaction commands are directed to data move operations, and vary from response expected commands by various bit values. Further, various commands specify transactions of only predetermined size (e.g., 16, 64, 256 response bytes).
While SCI can provide a scalable interface for multiprocessor based systems, it is always desirable to increase performance in a system, particular the rate at which requests may be processed in the case of a search engine system.